1. Field of the Invention
The present invention is related to a multilayered printed wiring board (hereinafter referred to as a multilayered PWB), which can be used for IC packaging with mounted electronic components such as IC chips.
2. Discussion of the Background
A built-up multilayered PWB is used as a substrate for, for example, IC packaging mounted with a semiconductor element for an MPU or the like. Those multilayered PWBs are formed as follows: On a core substrate made with a resin material with core material (such as a glass epoxy resin), a interlaminar insulation material without core material (such as a resin made mainly with epoxy resin) is laminated, and non-through-hole via holes are formed by a laser or the like; inside the via holes, conductor layers are deposited by performing plating or the like to electrically connect the core substrate and the conductor layers on the interlaminar insulation layers; and on the surfaces, solder bumps and solder layers are formed to mount an IC chip, electronic components or the like. Full-additive methods and semi-additive methods are used for the above.
Also, multilayered PWBs are formed as follows: Copper-laminated insulation layers as an insulation material are laminated and non-through-hole via holes are formed by a laser or the like; inside the via holes, conductor layers are formed by plating or with paste for electrical connections; and on the surfaces, solder bumps and solder layers are formed to mount IC chips, electronic components or the like. For example, Japanese Patent Laid-Open Publication Hei 5-029760 is directed to a process to build up insulation layers on a core substrate, and Japanese Patent Laid-Open Publication Hei 7-33991 is directed to resin compound for interlaminar insulation layers. The contents of the above mentioned publications are incorporated herein by reference in their entirety.